1 errata ? power consumption when using slowly rising power supply releasing reset condition without clock wake-up from power-save executes instructions before interrupt spi can send wrong byte wrong clearing of extrf in mcusr reset during eeprom write spi interrupt flag can be undefined after reset skip instruction with interrupts signature bytes read back value during eeprom polling miso active during in-system programming the adc has no free-running mode uart loses synchronization if rxd line is low when uart receive is disabled 13. power consumption when using slowly rising power supply if the power supply rises slowly upon start-up (slower than 10 ms rise time), the power consumption in sleep modes may exceed the specification. problem fix/workaround the device behaves functionally correct, and no actions need to be taken if power consumption is acceptable. to reduce power consumption, make sure the power supply has a sufficiently fast rise time. 12. releasing reset condition without clock if an external reset or a watchdog reset occurs while the clock is stopped and the reset is released before the clock is restarted, the internal reset will time-out after the start-up delay which is independent of the external clock. if no external clock pulses are present in the period when internal reset is active, the reset does cor- rectly cause tri-stating of the i/o while the reset is held. however, if the internal reset is released before the clock starts running, the part does not clear i/o regis- ters, nor set pc to 0x00. here, stopping the clock refers to gating the external clock input. power-down and power-save mode do not have this issue. problem fix/workaround make sure the clock is running whenever an external reset can be expected. if the watchdog is used, never stop an external clock. 11. wake-up from power-save executes instructions before interrupt when waking up from power-save, some instructions are executed before the interrupt is called. if the device is woken up by an external interrupt, two instruc- tion cycles are executed. if it is woken up by the asynchronous timer, three instructions are executed before the interrupt. problem fix/workaround make sure that the first two or three instructions following sleep are not dependent on the executed interrupt. 10. the spi can send wrong byte if the spi is in master mode, it will restart the old transfer if new data is written on the same clock edge as the previous transfer is finished. problem fix/workaround when writing to the spi, first wait until it is ready, then write the byte to transmit. 8-bit microcontroller with 128k bytes in-system programmable flash atmega103(l) rev. l errata sheet rev. 1436c?09/01
2 atmega103(l) errata 1436c?09/01 9. wrong clearing of extrf in mcusr the extrf flag in mcusr will be cleared when clearing the porf-flag. the flag does not get cleared by writing a ?0? to it. problem fix/workaround finish the test of both flags before clearing any of them. clear both flags simultaneously by writing ?0? to both porf and extrf in mcucr. 8. reset during eeprom write if reset is activated during eeprom write, the result is not what should be expected. the eeprom write cycle com- pletes as normal, but the address registers are reset to 0. the result is that both the address written and address 0 in the eeprom can be corrupted. problem fix/workaround avoid using address 0 for storage, unless you can guarantee that you will not get a reset during eeprom write. 7. spi interrupt flag can be undefined after reset in certain cases when there are transitions on the sck pin during reset, or the sck pin is left unconnected, the start-up value of the spi interrupt flag is unknown. if the flag is not reset before enabling the spi interrupt, a pending spi inter- rupt may be executed. problem fix/workaround clear the spi interrupt flag before enabling the interrupt. 6. skip instruction with interrupts a skip instruction (sbrs, sbrc, sbis, sbic, cpse) that skips a two-word instruction needs three clock cycles. if an interrupt occurs during the first or second clock cycle of this skip instruction, the return address will not be stored cor- rectly on the stack. in this situation, the address of the second word in the two-word instruction is stored. this means that on return from interrupt, the second word of the two-word command will be decoded and executed as an instruc- tion. the atmega103 has four two-word instructions: lds, sts, jmp, and call. notes: 1. this can only occur if all of the following conditions are true: - a skip instruction is followed by a two-word instruction. - the skip instruction is actually skipping the two-word instruction. - interrupts are enabled, and at least one interrupt source can generate an interrupt. - an interrupt arrives in the first or second cycle of the skip instruction. 2. this will only cause problems if the address of the following lds or sts command points to an address beyond 400 hex. problem fix/workaround for assembly program, avoid skipping a two-word instruction if interrupts are enabled. the following c-compilers handles this sequence correctly: - iar compiler, version 1.40b or higher - image craft compiler, all versions - codevision compiler, version 1.0.0.5 or higher 5. signature bytes the signature bytes of the first few lots of the atmega103 have been shipped with wrong signature bytes. also in the datasheet, the wrong signature bytes have been given. the correct signature bytes are: $1e $97 $01. problem fix/workaround programmers must allow both $1e $97 $01 and $1e $01 $01 as valid signature bytes.
3 atmega103(l) errata 1436c?09/01 4. read back value during eeprom polling when a new eeprom byte is being pr ogrammed into the eeprom with in -system programming, reading the address location being programmed will give the value p1 (see table below) until the auto-erase is finished. then the value p2 will follow until programming is finished. at the time the device is ready for a new eeprom byte, the pro- grammed value will read correctly. note: this is only a problem for in-system programmers. reading and writing the eeprom during normal operation is not affected by this. problem fix/workaround programmers must allow both $80 and $7f as read back values if data polling is used for the eeprom. polling will not work for either of the values p1 and p2, so when programming these values, the user will have to wait the prescribed time t wd_eeprom before programming the next byte. 3. miso active during in-system programming during in-system programming, the miso line (pin 13) of the atmega103 is active, although the uart pins are used for programming. if pin 13 is used as an input in the application, a collision may occur on this line. problem fix/workaround - if the miso pin is used as an input, make sure that there is a current-limiting resistor in series with the line. - if the pin is used as an output, make sure that whatever is connected to the line can accept that the pin is toggling during programming. 2. the adc has no free-running mode early versions of the atmega603/103 datasheet described an adc free-running mode. this mode is not available in this device, and bit number 5 in the adcsr register must always be written as ?0?. problem fix/workaround use single-conversion mode and always use the latest revision of the datasheet. 1. uart loses synchronization if rxd line is low when uart receive is disabled the uart will detect a uart start bit and start reception even if the uart is not enabled. if this occurs, the first byte after re-enabling the uart will be corrupted. problem fix/workaround make sure that the rx line is high at start-up and when the uart is disabled. an external rs-232 level converter keeps the line high during start-up. revision p1 p2 f$7f$7f g$80$7f j$80$7f k$80$7f l$80$7f
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